1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing a semiconductor device, and more particular it relates to a semiconductor device that is suitable for use as a DRAM and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
The level of integration of DRAMs has been undergoing an evolution of generations amounting to a 4-fold increase every 3 years. For this reason, there is a 0.7 shrinkage the minimum design feature each generation. The surface area of memory cells used to store information is undergoing a 0.4 shrinkage each generation. A simple squaring of this 0.7 ratio, without changing the memory cell layout, means that the surface area ratio should be approximately 0.5. In reality, however, the shrinkage ratio is 0.4. To achieve this, it is necessary to change the memory cell layout. One method of doing that requires the design margin with respect to contacts between interconnects to be made smaller. If the design margin between interconnects and contacts is made smaller and contacts are formed by the same method that was used in the past, manufacturing variations in, for example, position in the lithography process cause a reduction in yield because of contact between interconnects and contacts. Because of this problem, a self-aligning contact method has been proposed as a method of forming contacts which do not make contact, even in the case in which the margin between interconnects and contacts is reduced. The inventers filed Japanese patent application No.09-174724 for that method, which will be hereinafter referred to as the prior art method. In subsequent experiments, however, problems developed in applying the prior art method to further reductions in the small size of the memory cell. These problems will be described, with reference made to FIG. 16 through FIG. 20.
A first silicon nitride film 41, having a film thickness of 100 nm, is deposited on a gate electrode 5 using the CVD method. Then, a CVD is used to deposit a second silicon nitride film, having a film thickness of 50 nm, over the entire surface, and anisotropic etching is performed so that the second silicon nitride film 42 remains only on the side surface of the gate electrode 5 and the first silicon nitride film 41. As a result, the surface of the gate electrode 5 is entirely covered by an insulation film. When this is done, etchback is done so as to reduce the thickness of the first silicon nitride film 41 to approximately 70 nm. What is important to note here is the formation of the second silicon nitride film 42. On the side surface of the gate electrode 5, the side surface of the second silicon nitride film 42, similar to the side surface of the gate electrode 5, is formed so as to be perpendicular to the main surface of the substrate. On the side surface of the first silicon nitride film 41, the upper part is formed so as to be rounded at the corner. Only the surface of the n-type diffusion layer 7 that is formed on the p-type silicon substrate 1 is exposed. Single-crystal silicon is selectively grown anisotropically onto only this exposed surface, in a manner that is perpendicular to the main substrate surface, the result being the formation of a selectively grown silicon epitaxy pad. When forming this selective silicon epitaxy pad, problems arise. Anisotropic growth is only in a direction that is perpendicular with respect to the main surface of the substrate (that is, vertical), and there is no growth in a direction that is parallel to the main surface of the substrate (that is, horizontal). This will be described with reference to FIG. 18. First, consider the initial growth stage (hereinafter referred to as the first stage). A word line is formed that extends from the upper part to the lower part as shown in FIG. 18(a). Therefore, there is no broadening in the horizontal direction in the cross-sectional view of FIG. 18(b) because of the wall formed by the second silicon nitride film 42. The horizontal direction in the plan view of FIG. 18(c), however, because there is no word line, it is possible to have growth in the horizontal direction, even at the first stage. If the selective silicon epitaxy growth is isotropic growth, a selective silicon epitaxy pad will broaden in all directions. In isotropic growth, neighboring selective Silicon epitaxy pads on the element separation insulation film 2 make contact with one another. The method of growth to avoid this contact is anisotropic growth, and even in the case in which there is no obstacle in the horizontal direction, the speed of growth is quite small. This anisotropic growth is performed as described below. Specifically, with a crystal orientation of the p-type silicon substrate 1 as the (100) plane, the (110) plane is taken as the crystal orientation for a direction that is perpendicular to or parallel to the word line. By reducing the amount of flow of disilane gas, which is the gas used for silicon growth, from 10 sccm, which is the condition for isotropic growth, to 2 sccm, the speed of grow of the (110) plan with respect to the (100) plane is approximately 1/20. By defining the growth stage in this manner, the first stage is taken as the growth up to a height that maintains a perpendicular shape with respect to the substrate main surface, this being growth of the selective silicon epitaxy pad up to the reference numeral 43 in FIG. 18. The second stage is the growth stage after the first growth stage, this being the growth up until the point at which the side surface of the second silicon nitride film is rounded. In the region of this rounded shoulder, as shown in FIG. 19(b), it is possible to have gradual broadening in the horizontal direction. It is precisely because the angle of the shoulder changes gradually that this means a gradual change of the crystal orientation at the growth edge from the (110) direction to the (111) direction. A facet plane 45 appears as a change in the crystal orientation at the growth edge from (100) to either the (111) plane or (311) plane. Because these facet planes, similar to the (110) plane, have a growth that is slower than the speed of growth of the (100) plane, growth of the selective silicon epitaxy pad in the height direction is suppressed. Therefore, not only is it not possible to control the height growth by the growth time, it also becomes difficult to even grow to the required height. If the growth is forced under weak conditions for anisotropic growth, as shown in FIG. 20(c) there will be broadening on the element separation insulation film 2, so that neighbors make contact with one another. If, instead of the second stage growth, which is shown in FIG. 19, a contact is formed after application of the prior art, because of the small height of the selective silicon epitaxy 44 in the second stage, it is not possible to achieve a structure such as shown in FIG. 5.
Accordingly, it is an object of the present invention to improve over the drawbacks of the prior art as described above, and in particular, when forming a pad by growing a silicon crystal on a semiconductor substrate anisotropically in a vertical direction with respect to the semiconductor substrate, to obtain accurate anisotropic growth. Another object of the present invention is to provide a method of manufacturing the above-noted semiconductor device.
It is yet another object of the present invention to provide a method of manufacturing a semiconductor device in which the parasitic capacitance of the bit line is made small, and the DRAM operating margin is made large.